| From: | Andres Freund <andres(at)anarazel(dot)de> |
|---|---|
| To: | Greg Burd <greg(at)burd(dot)me> |
| Cc: | Thomas Munro <thomas(dot)munro(at)gmail(dot)com>, Nathan Bossart <nathandbossart(at)gmail(dot)com>, Peter Eisentraut <peter(at)eisentraut(dot)org>, PostgreSQL Hackers <pgsql-hackers(at)lists(dot)postgresql(dot)org>, Dave Cramer <davecramer(at)gmail(dot)com> |
| Subject: | Re: [PATCH] Fix ARM64/MSVC atomic memory ordering issues on Win11 by adding explicit DMB barriers |
| Date: | 2025-11-23 15:55:21 |
| Message-ID: | zhkahjuj5bvpxqp75qfib4wiaxnlahu6aopxhqsbkogqqxyuvp@j7tdvqtqm4lp |
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| Lists: | pgsql-hackers |
Hi,
On 2025-11-22 16:43:30 -0500, Greg Burd wrote:
> With the new MSVC compiler flag Andres mentioned (/arch:armv9.4) I only
> had to update the S_UNLOCK() macro, the compiler did the rest correctly
> AFAICT.
Just to be clear - the flag shouldn't be necessary for things to work
correctly. I was only using it to have godbolt inline the intrinsics, rather
than have them generate an out-of-line function call that I couldn't easily
inspect. I'm fairly sure that the out-of-line functions also have the relevant
barriers.
> @@ -2509,7 +2513,10 @@ int main(void)
> }
> '''
>
> - if cc.links(prog, name: '__crc32cb, __crc32ch, __crc32cw, and __crc32cd without -march=armv8-a+crc',
> + if cc.get_id() == 'msvc'
> + cdata.set('USE_ARMV8_CRC32C', 1)
> + have_optimized_crc = true
Should have a comment explaining why we can do this unconditionally...
Greetings,
Andres Freund
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