Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

On Thu, Aug 14, 2025 at 11:29:08AM +0200, Álvaro Herrera wrote:
> On 2025-May-01, Tom Lane wrote:
>> One other thing that comes to mind is that pg_stat_statements
>> has stretched the intention of "short straight-line code segment"
>> to the point of unrecognizability. Maybe it needs to stop using
>> spinlocks to protect pgssEntry updates. But I'm not sure if that
>> would move the needle on whether ISB is a good idea or not.
>
> Yeah, it looks like pgss_store() is being too generous on the amount of
> code run with that spinlock held. However, changing that spinlock to an
> lwlock doesn't look easy, because of the way each pgss entry is created
> as a dynahash entry, and then deallocated from there. With spinlocks we
> can just reinit the spinlock each time, but that doesn't work with
> lwlocks. We have no easy way to associate then disassociate each entry
> from a specific lwlock.

I've attempted multiple times now to replace this spinlock with LWLocks or
atomics, but thus far haven't produced anything that improved matters [0].
IIRC I just dynamically created LWLocks with LWLockInitialize() as needed,
which is tedious but easy enough. My recollection is that the use of
floats for many of the values greatly complicated the atomics attempts.
So, fixing it might require some larger changes.

[0] https://postgr.es/m/Zs4hJ6-Fg8DMgU_P%40nathan

--
nathan