| From: | "Devulapalli, Raghuveer" <raghuveer(dot)devulapalli(at)intel(dot)com> |
|---|---|
| To: | John Naylor <johncnaylorls(at)gmail(dot)com>, Andy Fan <zhihuifan1213(at)163(dot)com> |
| Cc: | Nathan Bossart <nathandbossart(at)gmail(dot)com>, Jesper Pedersen <jesperpedersen(dot)db(at)gmail(dot)com>, Tomas Vondra <tomas(at)vondra(dot)me>, "pgsql-hackers(at)lists(dot)postgresql(dot)org" <pgsql-hackers(at)lists(dot)postgresql(dot)org>, "Shankaran, Akash" <akash(dot)shankaran(at)intel(dot)com> |
| Subject: | RE: Improve CRC32C performance on SSE4.2 |
| Date: | 2025-06-17 16:19:49 |
| Message-ID: | PH8PR11MB82865BCE94C409E283CF6AFAFB73A@PH8PR11MB8286.namprd11.prod.outlook.com |
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| Lists: | pgsql-hackers |
> In case Andy is asking about "how" rather than "under what circumstances", my
> guess is: -O1+ may have just chosen instructions that also happen to zero-extend,
> which are common. -O0 doesn't represent the naive straightforward structure of
> what the programmer wrote, it's more like an "exploded" representation suitable
> for later optimization passes. That's why it always looks goofy.
Hah yeah. I missed the "how" part of the question but your explanation makes sense.
> > > Replacing that with _mm512_zextsi128_si512 fixes the problem.
>
> Here's a patch for testing, which also reverts the previous workaround. Help
> welcome, but I still promise to test it in the near future regardless.
LGTM.
Raghuveer
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