| From: | John Naylor <johncnaylorls(at)gmail(dot)com> |
|---|---|
| To: | Lukas Fittl <lukas(at)fittl(dot)com> |
| Cc: | Andres Freund <andres(at)anarazel(dot)de>, Jakub Wartak <jakub(dot)wartak(at)enterprisedb(dot)com>, Hannu Krosing <hannuk(at)google(dot)com>, Robert Haas <robertmhaas(at)gmail(dot)com>, Pavel Stehule <pavel(dot)stehule(at)gmail(dot)com>, vignesh C <vignesh21(at)gmail(dot)com>, Michael Paquier <michael(at)paquier(dot)xyz>, Ibrar Ahmed <ibrar(dot)ahmad(at)gmail(dot)com>, Maciek Sakrejda <m(dot)sakrejda(at)gmail(dot)com>, pgsql-hackers <pgsql-hackers(at)postgresql(dot)org>, David Geier <geidav(dot)pg(at)gmail(dot)com> |
| Subject: | Re: Reduce timing overhead of EXPLAIN ANALYZE using rdtsc? |
| Date: | 2026-04-03 09:06:14 |
| Message-ID: | CANWCAZbJfyoX-e5gxMBKBb=04FBDz_pTsqb4Poij_AHiu29K9g@mail.gmail.com |
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| Lists: | pgsql-hackers |
On Fri, Apr 3, 2026 at 6:16 AM Lukas Fittl <lukas(at)fittl(dot)com> wrote:
> v16
Just some minor quibbles on 0002:
--- a/src/include/port/pg_cpu.h
+++ b/src/include/port/pg_cpu.h
@@ -23,6 +23,12 @@ typedef enum X86FeatureId
/* scalar registers and 128-bit XMM registers */
PG_SSE4_2,
PG_POPCNT,
+ PG_HYPERVISOR,
The hypervisor flag doesn't really belong with an instruction family.
Maybe a separate category like "identification"?
+ /* TSC flags */
+ PG_RDTSCP,
+ PG_TSC_INVARIANT,
+ PG_TSC_ADJUST,
Maybe spell out time stamp counter in the comment, since this will be
the first time the reader encounters that in this file.
+ * For some other Hypervisors that have an invariant TSC, e.g. HyperV, we would
+ * need to access an MSR to get the frequency (which is typically not available
Maybe spell out MSR too, because I for one don't know what that is.
+ X86Features[PG_HYPERVISOR] = reg[ECX] >> 31 & 1;
+ have_osxsave = reg[ECX] & (1 << 27);
+
+ pg_cpuid_subleaf(0x07, 0, reg);
+
+ X86Features[PG_TSC_ADJUST] = (reg[EBX] & (1 << 1)) != 0;
Some inconsistency in shift style.
--
John Naylor
Amazon Web Services
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