On Mon, 23 Jan 2023 at 05:06, John Naylor <john(dot)naylor(at)enterprisedb(dot)com> wrote:
>
> According to Agner's instruction tables [1], integer division on Skylake (for example) has a latency of 26 cycles for 32-bit operands, and 42-95 cycles for 64-bit.
>
> [1] https://www.agner.org/optimize/instruction_tables.pdf
>
Thanks, that's a very useful reference.
(And I do indeed have one of those CPUs, which explains what I was seeing.)
Regards,
Dean