Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

Nathan Bossart <nathandbossart(at)gmail(dot)com> writes:
> On Thu, Jun 19, 2025 at 12:10:52PM -0700, Salvatore Dipietro wrote:
>> We can notice that with low concurrency (1,2,4) results are similar
>> while with medium concurrency (8,16)
>> the No-ISB approach can introduce some regression especially on
>> smaller instances. However, we can see some significant
>> positive performance impact with high concurrency (>=32) settings on
>> large instances (up to 8.76x on m7g.16xl with 256 concurrency).

> Given these mixed results, it's unclear to me how exactly we should
> proceed. Perhaps there is another approach that reduces the regressions to
> a negligible level while still producing gains at higher levels of
> concurrency. Or maybe we can convince ourselves that these regressions
> aren't worth worrying about, but that seems like a bit of a stretch to me.

I agree; I'm also worried that this may be optimizing for one
particular ARM implementation and have negative effects on others.

Perhaps a better way forward is to identify which spinlock is
suffering such huge contention and try to alleviate that at a
higher design level. (That could benefit more than just ARM, too.)

regards, tom lane