Re: 7.1 vs. 7.2 on AIX 5L

> > What is "isync"? Also, how I can implement calling
>
> sorry no idea :-(
>
> > compare_and_swap in the assembly language?
>
> In assembly language you would do the locking yourself,
> the code would be identical, or at least very similar to
> the __APPLE__ __ppc__ code.
>
> sample lock code supplied in the PowerPC
> Architecture book (page 254):
>
> unlock: sync
> stw 0, lock_location
> blr
>
> In the unlock case the sync is all that is necessary to make all changes
> protected by the lock globally visible. Note that no lwarx or stwcx. is
> needed.
>
> lock:
> 1: lwarx r5, lock_location
> cmpiw r5, 0
> bne 2f:
> stwcx. 1, lock_location
> bne 1b
> isync
> blr
> 2: need to indicate the lock is already locked (could spin if you want to
> in this case or put on a sleep queue)
> blr
>
> isync only affects the running processor.

I have tried LinuxPPC's TAS code but AIX's assembler complains that
lwarx and stwcx are unsupported op. So it seems that we need to tweak
your code actually.
--
Tatsuo Ishii