Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

From: Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us>
To: Nathan Bossart <nathandbossart(at)gmail(dot)com>
Cc: Robert Haas <robertmhaas(at)gmail(dot)com>, Salvatore Dipietro <dipietro(dot)salvatore(at)gmail(dot)com>, pgsql-hackers(at)postgresql(dot)org, Salvatore Dipietro <dipiets(at)amazon(dot)com>, blakgeof(at)amazon(dot)com
Subject: Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture
Date: 2025-05-01 20:08:06
Message-ID: 1650263.1746130086@sss.pgh.pa.us
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Nathan Bossart <nathandbossart(at)gmail(dot)com> writes:
> ... commit 3d0b4b1 recently added a non-locking
> initial test in AArch64's TAS_SPIN, so I wonder if the ISB is still
> appropriate. It'd be interesting to see the performance difference of
> removing the ISB with and without commit 3d0b4b1 applied.

Oh! That's an excellent point. The OP didn't mention if their tests
were done before or after 3d0b4b1, but that might well matter.

I still think pgbench is a very blunt tool for this type of testing,
though. I recommend resurrecting the test_shm_mq-based hack discussed
in the prior thread and seeing what that shows.

regards, tom lane

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