Re: Re: [PATCH] Use CC atomic builtins if available [was: Re: TAS patch for building on armel/armhf thumb]

On Mon, Dec 19, 2011 at 11:25:06PM +0200, Heikki Linnakangas wrote:
> I compiled the attached test program on an HP Itanium box, using the
> same flags you get from PostgreSQL's configure on that box. The relevant
> assembler output is:
>
> xchg4 r14 = [r15], r14 // M [slocktest.c: 66/3]
> //file/line/col slocktest.c/67/3
> ld1.acq r16 = [r11] // M [slocktest.c: 67/3]
> nop.i 0 // I
> //file/line/col slocktest.c/68/3
> st1.rel [r11] = r10 ;; // M [slocktest.c: 68/3]
> //file/line/col slocktest.c/69/3
> st4.rel [r15] = r0 // M [slocktest.c: 69/3]
> //file/line/col slocktest.c/70/1
>
>
> The trick I missed is that the compiler attaches .rel to all the stores
> and .acq to all the loads through a volatile pointer. gcc seems to do
> the same. So we're safe.

The Intel compiler appears not to follow this convention:
http://software.intel.com/sites/products/documentation/hpc/compilerpro/en-us/cpp/lin/compiler_c/copts/ccpp_options/option_qserialize-volatile.htm

If you have that compiler installed, could you see which opcode it generates?

Thanks,
nm