From: | Kenneth Marshall <ktm(at)it(dot)is(dot)rice(dot)edu> |
---|---|
To: | Simon Riggs <simon(at)2ndquadrant(dot)com> |
Cc: | Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us>, pgsql-hackers <pgsql-hackers(at)postgresql(dot)org> |
Subject: | Re: LWLock cache line alignment |
Date: | 2005-02-03 15:42:20 |
Message-ID: | 20050203154220.GD2584@it.is.rice.edu |
Views: | Raw Message | Whole Thread | Download mbox | Resend email |
Thread: | |
Lists: | pgsql-hackers |
On Thu, Feb 03, 2005 at 06:26:16AM -0800, Simon Riggs wrote:
> > From: Tom Lane [mailto:tgl(at)sss(dot)pgh(dot)pa(dot)us] wrote
> > "Simon Riggs" <simon(at)2ndquadrant(dot)com> writes:
> > > It looks like padding out LWLock struct would ensure that
> > each of those
> > > were in separate cache lines?
> >
> > I've looked at this before and I think it's a nonstarter;
> > increasing the
> > size of a spinlock to 128 bytes is just not reasonable.
> > (Remember there
> > are two per buffer.)
>
> Well, the performance is unreasonably poor, so its time to do something,
> which might if it is unreasonable for the general case would need to be
> port specific.
>
> Also, there's no evidence it would actually help
> > anything, because the contention we have been able to measure
> > is on only
> > one particular lock (BufMgrLock) anyway. But feel free to
> > try it to see
> > if you can see a difference.
>
> Well, the Wierd Context Switching issue isn't normal contention, which I
> agree is stacked up against BufMgrLock.
>
> Overlapping cache lines doesn't cause measurable user space contention,
> just poor performance when the delay for cache-spoil, refetch is
> required many times more than the minimum (ideal).
>
> I'm thinking that the 128 byte cache line on Intel is sufficiently
> higher than the 64 byte cache line on AMD to tip us into different
> behaviour at runtime.
>
Would it be possible to "randomize" the placement of the LWLock
struct to reduce lock correlation in the buffers. i.e. Ensure that
buffer locks and allocated at least 1 cacheline apart. This may
allow the reduction in cache coherency and still maintain a compact
data structure. Maybe a simple mod X offset?
Ken
From | Date | Subject | |
---|---|---|---|
Next Message | Martin Pitt | 2005-02-03 15:58:28 | Re: libpq API incompatibility between 7.4 and 8.0 |
Previous Message | Neil Conway | 2005-02-03 14:42:48 | Re: LWLock cache line alignment |