Intel(R) Memory Latency Checker - v3.12
*** Unable to modify prefetchers (try executing 'modprobe msr')
*** So, enabling random access for latency measurements
Measuring idle latencies for random access (in ns)...
		Numa node
Numa node	     0	     1	
       0	 129.9	 129.9	
       1	 128.3	 128.1	

Measuring Peak Injection Memory Bandwidths for the system
Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
Using all the threads from each core if Hyper-threading is enabled
Using traffic with the following read-write ratios
ALL Reads        :	233023.4	
3:1 Reads-Writes :	267684.9	
2:1 Reads-Writes :	275930.3	
1:1 Reads-Writes :	292524.8	
Stream-triad like:	273671.9	
All NT writes    :	170797.1	
1:1 Read-NT write:	292916.6	

Measuring Memory Bandwidths between nodes within system 
Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
Using all the threads from each core if Hyper-threading is enabled
Using Read-only traffic type
		Numa node
Numa node	       0	       1	
       0	123198.1	117550.5	
       1	119335.1	116650.4	

Measuring Loaded Latencies for the system
Using all the threads from each core if Hyper-threading is enabled
Using Read-only traffic type
Inject	Latency	Bandwidth
Delay	(ns)	MB/sec
==========================
 00000	721.29	232845.2
 00002	664.14	232818.5
 00008	664.32	232741.6
 00015	662.87	232813.0
 00050	658.94	232603.5
 00100	654.70	232538.6
 00200	175.42	211784.1
 00300	158.98	143574.0
 00400	154.97	105691.8
 00500	152.84	 85336.8
 00700	151.05	 61592.4
 01000	149.91	 43717.3
 01300	150.28	 33896.4
 01700	142.11	 26119.2
 02500	142.59	 17949.0
 03500	152.47	 12940.1
 05000	140.65	  9230.0
 09000	141.48	  5332.5
 20000	140.18	  2654.3

Measuring cache-to-cache transfer latency (in ns)...
Local Socket L2->L2 HIT  latency	25.3
Local Socket L2->L2 HITM latency	25.3